IEEE

Improving LLM-Based Verilog Code Generation with Data Augmentation and RL

Abstract: Large language models (LLMs) have recently attracted significant attention for their potential in Verilog code generation. However, existing LLM-based methods face several challenges, ...
IEEE

Design and Implementation of Universal Asynchronous Receiver/Transmitter (UART): A Review

Abstract: The Universal Asynchronous Receiver/Transmitter (UART) continues to be a fundamental element of serial communication within embedded systems and IoT, valued for its straightforwardness and ...
GitHub

BrahmaGanesh/uart_protocol_verification

This repository contains a SystemVerilog verification environment for a UART protocol implementation. The self-checking testbench generates randomized byte transactions, drives them through the DUT ...
GitHub

A drone with a wide-band RFSoC-based transmitter and an RFSoC-based receiver to map the antenna pattern of a radio telescope

We designed and tested a drone with a wide-band transmitter (down to 30 MHz up to to 1.8 GHz) to measure the complex antenna pattern of radio telescopes. We basically split a VNA in half and flew one ...