EDN

System Verilog configurable coverage model in an OVM setup – concept of reusability

With the advent of a new era in verification technology based on an advanced HVL like System Verilog, the concept of random stimulus based verification was born, to verify today’s multi‐million gate ...
Design-Reuse

Transaction Recording, Modeling and Extensions for SystemVerilog

Adoption of transaction level modeling and the necessary tools for debugging and analysis has been slower than would be expected from growing SOC design sizes and complexities. This paper discusses ...
Design-Reuse

A SystemVerilog DPI Framework for Reusable Transaction Level Testing, Debug and Analysis of SoC Designs

Complex system design requires modeling, testing, debug and analysis of many levels of abstraction with varying levels of accuracy. Reuse from previous steps is important at each step of the design ...
EDN

DESIGN AUTOMATION: Virtual prototype support rolls out

Santa Cruz, Calif. — Targeting an emerging niche within electronic system-level (ESL) design, Bluespec Inc. this week will roll out a new version of its Bluesim simulator that supports virtual ...
Electronic Design

Boost Analog Design Model Accuracy

This file type includes high-resolution graphics and schematics when applicable. Rinkesh Patel, Senior Design Verification Engineer, Microsoft Corp. Verifying analog and mixed-signal circuits in ...
Electronic Design

Formal Methodology Validates Cache-Coherence Protocol

Bugs in RTL code are problematic, but a bug in an architectural specification can be catastrophic. If the bug remains undetected until post-silicon debugging, the design process essentially starts all ...